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22nd IEEE VLSI Test Symposium
Napa Valley, California
April 25-April 29
ISBN: 0-7695-2134-7
Table of Contents
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Plenary Session
Welcome Address: Andre Ivanov
Keynote Address
Program Introduction: Irith Pomeranz
Invited Address
Awards Presentations
1A: Paper Session - Defect-Oriented Testing
E. J. McCluskey, Stanford Center for Reliable Computing
Ahmad Al-Yamani, Stanford Center for Reliable Computing
James C.-M Li, Stanford Center for Reliable Computing
Chao-Wen Tseng, Stanford Center for Reliable Computing
Erik Volkerink, Stanford Center for Reliable Computing
Francois-Fabien Ferhani, Stanford Center for Reliable Computing
Edward Li, Stanford Center for Reliable Computing
Subhasish Mitra, Stanford Center for Reliable Computing
pp. 16
Srikanth Venkataraman, Intel Corporation, Hillsboro, OR
Srihari Sivaraj, Intel Corporation, Hillsboro, OR
Enamul Amyeen, Intel Corporation, Hillsboro, OR
Sangbong Lee, Intel Corporation, Hillsboro, OR
Ajay Ojha, Intel Corporation, Hillsboro, OR
Ruifeng Guo, Intel Corporation, Hillsboro, OR
pp. 23
1B: Paper Session - Delay Testing
Wangqi Qiu, Texas A&M University, College Station
Xiang Lu, Texas A&M University, College Station
Jing Wang, Texas A&M University, College Station
Zhuo Li, Texas A&M University, College Station
D. M. H. Walker, Texas A&M University, College Station
Weiping Shi, Texas A&M University, College Station
pp. 37
Subhasish Mitra, Intel Corporating, Sacramento, CA; Stanford University, CA
Erik Volkerink, Stanford University, CA
Edward J. McCluskey, Stanford University, CA
Stefan Eichenberger, Philips Semiconductors, Nijmegen, The Netherlands
pp. 43
1C: Innovative Practices Session - Silicon Debug and Diagnosis
Debugging Complex Digital System Chips with Embedded Software: Challenges and Opportunities
A Universal Diagnosis Tool
Scan Dump Tracer
2A: Paper Session - Current Based Testing
Josep Rius V?zquez, Universitat Polit?cnica de Catalunya, Spain
Jos? Pineda de Gyvez, Philips Research Laboratories, The Netherlands
pp. 53
Sagar Sabade, Texas A&M University, College Station
D. M. H. Walker, Texas A&M University, College Station
pp. 65
2B: Paper Session - Test Data Compression and Low-Speed ATE
Nodari Sitchinava, Synopsys Inc., Mountain View, CA
Samitha Samaranayake, Massachusetts Institute of Technology, Cambridge, MA
Rohit Kapur, Synopsys Inc., Mountain View, CA
Emil Gizdarski, Synopsys Inc., Mountain View, CA
Fredric Neuveux, Synopsys Inc., Mountain View, CA
T. W. Williams, Synopsys Inc., Mountain View, CA
pp. 73
Michael Nelms, IBM Microelectronics Division, Essex Junction, VT
Kevin Gorman, IBM Microelectronics Division, Essex Junction, VT
Darren Anand, IBM Microelectronics Division, Essex Junction, VT
pp. 87
2C: Innovative Practices Session - Practical Experience with Test and Repair of Large Memory Systems
Memory Test and Repair for a Large Design
A Practical Experience of Implementing Memory Repair in COT
ATE Memory Repair Methodologies - Tradeoffs and Trends
3A: Paper Session - Pattern Debug, Yield Analysis and FPGA Testing
Debashis Nayak, Intel Corporation, Hillsboro, OR
Srikanth Venkataraman, Intel Corporation, Hillsboro, OR
Paul Thadikaran, Intel Corporation, Hillsboro, OR
pp. 97
D. Appello, ST Microelectronics, Cornaredo, Italy
A. Fudoli, ST Microelectronics, Cornaredo, Italy
K. Giarda, ST Microelectronics, Cornaredo, Italy
E. Gizdarski, Synopsys Inc., Mountain View, CA
B. Mathew, Synopsys Inc., Mountain View, CA
V. Tancorre, ST Microelectronics, Cornaredo, Italy
pp. 103
3B: Paper Session - Memory Testing I
Zaid Al-Ars, Delft University of Technology, The Netherlands
Said Hamdioui, Delft University of Technology, The Netherlands
Ad J. van de Goor, Delft University of Technology, The Netherlands
pp. 117
Mohamed Azimane, Philips Research Laboratories, Eindhoven, The Netherlands
Ananta K. Majhi, Philips Research Laboratories, Eindhoven, The Netherlands
pp. 123
L. Dilillo, Universit? de Montpellier II / CNRS, France
P. Girard, Universit? de Montpellier II / CNRS, France
S. Pravossoudovitch, Universit? de Montpellier II / CNRS, France
A. Virazel, Universit? de Montpellier II / CNRS, France
S. Borri, Infineon Technologies France
pp. 129
3C: Innovative Practices Session - Test Compression
Economic Considerations for Scan Test Compression
XPAND + X-COMPACT: Key Learnings
Use of Compression for High Quality Delay Testing
4A: Paper Session - MEMs Testing and FPGA Testing
Nilmoni Deb, Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA
pp. 139
Xingguo Xiong, University of Cincinnati, OH
Yu-Liang Wu, The Chinese University of Hong Kong, Shattin
Wen-Ben Jone, University of Cincinnati, OH
pp. 148
4B: Embedded Tutorial Session - Challenges in Embedded Memory Test and Diagnosis
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4C: Innovative Practices Session - ITRS Key Challenge: High Speed I/Os
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5A: Embedded Tutorial Session - Advances in Wafer Probe Test
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5B: HotTopic Session - Testing of Nanocircuits with High Defect Densities
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6A: Paper Session - Low-Voltage and Thermal Testing
Piet Engelke, Albert-Ludwigs-University, Germany
Ilia Polian, Albert-Ludwigs-University, Germany
Michel Renovell, LIRMM - UMII, France
Bharath Seshadri, Purdue University, W. Lafayette, IN
Bernd Becker, Albert-Ludwigs-University, Germany
pp. 171
J. Altet, Universitat Polit?cnica de Catalunya, Barcelona, Spain
A. Rubio, Universitat Polit?cnica de Catalunya, Barcelona, Spain
A. Salhi, Universit? Bordeaux I, Bordeaux, France
J. L. G?lvez, Universitat Polit?cnica de Catalunya, Barcelona, Spain
S. Dilhaire, Universit? Bordeaux I, Bordeaux, France
A. Syal, The University of British Columbia. Vancouver. Canada
A. Ivanov, The University of British Columbia. Vancouver. Canada
pp. 179
Ethan Long, Portland State University, Oregon
W. Robert Daasch, Portland State University, Oregon
Robert Madge, LSI Logic, Gresham
Brady Benware, LSI Logic, Fort Collins
pp. 185
6B: Paper Session - Logic Built-In Self-Test
Grzegorz Mrugalski, Mentor Graphics Corporation, Wilsonville, OR
Nilanjan Mukherjee, Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR
Jerzy Tyszer, Poznan University of Technology, Poland
pp. 193
Liyang Lai, University of Illinois at Urbana-Champaign
Thomas Rinderknecht, Mentor Graphics Corp., OR
Wu-Tung Cheng, Mentor Graphics Corp., OR
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 199
S. Manich, Universitat Polit?cnica de Catalunya, Spain
L. Garc?, Universitat Polit?cnica de Catalunya, Spain
L. Balado, Universitat Polit?cnica de Catalunya, Spain
E. Lupon, Universitat Polit?cnica de Catalunya, Spain
J. Rius, Universitat Polit?cnica de Catalunya, Spain
R. Rodr?guez, Universitat Polit?cnica de Catalunya, Spain
J. Figueras, Universitat Polit?cnica de Catalunya, Spain
pp. 206
6C: Innovative Practices Session - Latest Results in WirelessTest
On-Chip RF Measurement Circuits
Bringing Wireless Test to the Mainstream
Test Environment and RF Test
7A: Paper Session - Analog Testing I
Qi Wang, University of Washington, Seattle
Yi Tang, University of Washington, Seattle
Mani Soma, University of Washington, Seattle
pp. 223
Soumendu Bhattacharya, Georgia Institute of Technology, Atlanta
Ganesh Srinivasan, Georgia Institute of Technology, Atlanta
Sasikumar Cherubal, Texas Instruments, Dallas, TX
Achintya Halder, Georgia Institute of Technology, Atlanta
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta
pp. 229
7B: Paper Session - Memory Testing II
Baosheng Wang, University of British Columbia, Vancouver, Canada
Josh Yang, University of British Columbia, Vancouver, Canada
James Cicalo, University of British Columbia, Vancouver, Canada
Andr? Ivanov, University of British Columbia, Vancouver, Canada
Yervant Zorian, Virage Logic Corporation
pp. 237
Xiaogang Du, University of Iowa, Iowa City
Sudhakar M. Reddy, University of Iowa, Iowa City
Don E. Ross, Mentor Graphics Corporation, Wilsonville, Oregon
Wu-Tung Cheng, Mentor Graphics Corporation, Wilsonville, Oregon
Joseph Rayhawk, Mentor Graphics Corporation, Wilsonville, Oregon
pp. 243
7C: Innovative Practices Session - SoC Test Practice in Japan
A Practical I{DDQ} Test Method for SoC Devices with mA Order I{DDQ}
The Application of Test Cost Reduction Method for High-End Products
SoC Test Strategy with Logic BIST
8A: Paper Session - Analog Testing II
Alberto Valdes-Garcia, Texas A&M University, College Station, TX
Jose Silva-Martinez, Texas A&M University, College Station, TX
Edgar S?nchez-Sinencio, Texas A&M University, College Station, TX
pp. 261
Chee-Kian Ong, University of California, Santa Barbara
Dongwoo Hong, University of California, Santa Barbara
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
Li-C Wang, University of California, Santa Barbara
pp. 267
8B: New Topic Session - Advances in 3D Packaging
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8C: Innovative Practices Session - Challenges
Yield Drive through Statistical Data Analysis
Targeting Systematic Defects Using Innovative Frequency Outlier Screening Methods?
Pseudo-Exhaustive Tests and Test Conditions for PPM Reduction in Memories
9A: Embedded Tutorial Session - Reliability & Dependability
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9B: Panel Session - Elevator Talks
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9C: Panel Session - Process Variation - How Severe Is the Problem of Design & Test
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10A: Paper Session - Defect Analysis and Fault Simulation
Mehdi Baradaran Tahoori, Northeastern University, Boston, MA
Mariam Momenzadeh, Northeastern University, Boston, MA
Jing Huang, Northeastern University, Boston, MA
Fabrizio Lombardi, Northeastern University, Boston, MA
pp. 291
Sounil Biswas, Carnegie Mellon University, Pittsburgh, PA
Kumar N. Dwarakanath, Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA
pp. 297
Abhishek Singh, University of Maryland, Baltimore County
Chintan Patel, University of Maryland, Baltimore County
Jim Plusquellic, University of Maryland, Baltimore County
pp. 304
10B: Paper Session - Issues in Reliability
Michael Nicolaidis, iRoC Technologies, Grenoble, France
Nadir Achouri, iRoC Technologies, Grenoble, France
Lorena Anghel, TIMA Laboratory, Grenoble, France
pp. 313
Sobeeh Almukhaizim, Yale University, New Haven, CT
Petros Drineas, Rensselaer Polytechnic Institute, Troy, NY
Yiorgos Makris, Yale University, New Haven, CT
pp. 319
Balkaran S. Gill, Case Western Reserve University, Cleveland, Ohio
Chris Papachristou, Case Western Reserve University, Cleveland, Ohio
Francis G. Wolff, Case Western Reserve University, Cleveland, Ohio
pp. 325
11A: Paper Session - Wireless and System Testing
Hans Eberle, Sun Microsystems Laboratories
Arvinderpal Wander, University of Michigan, Ann Arbor
Nils Gura, Sun Microsystems Laboratories
pp. 335
Brian Moore, BigBangWidth, Inc.
Chris Backhouse, University of Alberta, Edmonton, Canada
Martin Margala, University of Rochester, New York
pp. 341
Tian-Wei Huang, National Taiwan University, Taipei
Pei-Si Wu, National Taiwan University, Taipei
Ren-Chieh Liu, National Taiwan University, Taipei
Jeng-Han Tsai, National Taiwan University, Taipei
Huei Wang, National Taiwan University, Taipei
Tzi-Dar Chiueh, National Taiwan University, Taipei
pp. 347
11B: Paper Session - System-on-Chip Testing
Erik Larsson, Link?pings Universitet, Sweden
Julien Pouget, Montpellier 2 University, France
Zebo Peng, Link?pings Universitet, Sweden
pp. 361
11C: Innovative Practices Session - The Impact of SER
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12A: Paper Session - Analog Testing and Design Validation
Ashwin Raghunathan, The University of Texas at Austin
Hong Joong Shin, The University of Texas at Austin
Jacob A. Abraham, The University of Texas at Austin
Abhijit Chatterjee, Georgia Institute of Technology
pp. 377
T. Balen, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
A. Andrade Jr., Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
F. Aza?, Universit? de Montpellier II, France
M. Lubaszewski, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil; Universidad de Sevilla, Spain
M. Renovell, Universit? de Montpellier II, France
pp. 383
12B: Embedded Tutorial Session - Design for Yield
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12C: Innovative Practices Session - Optimizing Manufacturing Process
How Can Design for Manufacturability Improve Mask Costs and Yields?
Collaboration through Industry Standards for Manufacturing Success
Enhancement to IEEE 1149.1 Enables Simplified Parallel Test of ICs
13A: Embedded Tutorial Session - Design for Manufacturability
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13B: Hot Topic Session - Software-based Embedded Test
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13C: Panel Session - Defect-based Testing and Burn-in: A Test Solution for Scaled Technology?
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