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- VTS
- 2004
- 22nd IEEE VLSI Test Symposium
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22nd IEEE VLSI Test Symposium Napa Valley, California April 25-April 29 ISBN: 0-7695-2134-7 Table of Contents
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| Plenary Session |
Welcome Address: Andre Ivanov
Program Introduction: Irith Pomeranz
| 1A: Paper Session - Defect-Oriented Testing |
Edward Li, Stanford Center for Reliable Computing pp. 16
| 1B: Paper Session - Delay Testing |
Xiang Lu, Texas A&M University, College Station
Jing Wang, Texas A&M University, College Station
Zhuo Li, Texas A&M University, College Station pp. 37
Subhasish Mitra, Intel Corporating, Sacramento, CA; Stanford University, CA pp. 43
| 1C: Innovative Practices Session - Silicon Debug and Diagnosis |
Debugging Complex Digital System Chips with Embedded Software: Challenges and Opportunities
A Universal Diagnosis Tool
| 2A: Paper Session - Current Based Testing |
C. Thibeault, Ecole de technologie superieure, Montreal, Canada pp. 59
| 2B: Paper Session - Test Data Compression and Low-Speed ATE |
Kevin Gorman, IBM Microelectronics Division, Essex Junction, VT
Darren Anand, IBM Microelectronics Division, Essex Junction, VT pp. 87
| 2C: Innovative Practices Session - Practical Experience with Test and Repair of Large Memory Systems |
Memory Test and Repair for a Large Design
A Practical Experience of Implementing Memory Repair in COT
ATE Memory Repair Methodologies - Tradeoffs and Trends
| 3A: Paper Session - Pattern Debug, Yield Analysis and FPGA Testing |
A. Fudoli, ST Microelectronics, Cornaredo, Italy
K. Giarda, ST Microelectronics, Cornaredo, Italy pp. 103
| 3B: Paper Session - Memory Testing I |
Zaid Al-Ars, Delft University of Technology, The Netherlands pp. 117
L. Dilillo, Universit? de Montpellier II / CNRS, France
P. Girard, Universit? de Montpellier II / CNRS, France
A. Virazel, Universit? de Montpellier II / CNRS, France pp. 129
| 3C: Innovative Practices Session - Test Compression |
Economic Considerations for Scan Test Compression
XPAND + X-COMPACT: Key Learnings
Use of Compression for High Quality Delay Testing
| 4A: Paper Session - MEMs Testing and FPGA Testing |
Nilmoni Deb, Carnegie Mellon University, Pittsburgh, PA pp. 139
Yu-Liang Wu, The Chinese University of Hong Kong, Shattin pp. 148
| 4B: Embedded Tutorial Session - Challenges in Embedded Memory Test and Diagnosis |
| 4C: Innovative Practices Session - ITRS Key Challenge: High Speed I/Os |
| 5A: Embedded Tutorial Session - Advances in Wafer Probe Test |
| 5B: HotTopic Session - Testing of Nanocircuits with High Defect Densities |
| 6A: Paper Session - Low-Voltage and Thermal Testing |
J. Altet, Universitat Polit?cnica de Catalunya, Barcelona, Spain
A. Rubio, Universitat Polit?cnica de Catalunya, Barcelona, Spain
A. Salhi, Universit? Bordeaux I, Bordeaux, France
J. L. G?lvez, Universitat Polit?cnica de Catalunya, Barcelona, Spain
A. Syal, The University of British Columbia. Vancouver. Canada
A. Ivanov, The University of British Columbia. Vancouver. Canada pp. 179
| 6B: Paper Session - Logic Built-In Self-Test |
Liyang Lai, University of Illinois at Urbana-Champaign pp. 199
S. Manich, Universitat Polit?cnica de Catalunya, Spain
L. Garc?, Universitat Polit?cnica de Catalunya, Spain
L. Balado, Universitat Polit?cnica de Catalunya, Spain
E. Lupon, Universitat Polit?cnica de Catalunya, Spain
J. Rius, Universitat Polit?cnica de Catalunya, Spain
J. Figueras, Universitat Polit?cnica de Catalunya, Spain pp. 206
| 6C: Innovative Practices Session - Latest Results in WirelessTest |
On-Chip RF Measurement Circuits
Bringing Wireless Test to the Mainstream
Test Environment and RF Test
| 7A: Paper Session - Analog Testing I |
Qi Wang, University of Washington, Seattle
Yi Tang, University of Washington, Seattle pp. 223
| 7B: Paper Session - Memory Testing II |
Josh Yang, University of British Columbia, Vancouver, Canada
James Cicalo, University of British Columbia, Vancouver, Canada
Andr? Ivanov, University of British Columbia, Vancouver, Canada pp. 237
Don E. Ross, Mentor Graphics Corporation, Wilsonville, Oregon pp. 243
| 7C: Innovative Practices Session - SoC Test Practice in Japan |
A Practical I{DDQ} Test Method for SoC Devices with mA Order I{DDQ}
The Application of Test Cost Reduction Method for High-End Products
SoC Test Strategy with Logic BIST
| 8A: Paper Session - Analog Testing II |
Li-C Wang, University of California, Santa Barbara pp. 267
| 8B: New Topic Session - Advances in 3D Packaging |
| 8C: Innovative Practices Session - Challenges |
Yield Drive through Statistical Data Analysis
Targeting Systematic Defects Using Innovative Frequency Outlier Screening Methods?
Pseudo-Exhaustive Tests and Test Conditions for PPM Reduction in Memories
| 9A: Embedded Tutorial Session - Reliability & Dependability |
| 9B: Panel Session - Elevator Talks |
| 9C: Panel Session - Process Variation - How Severe Is the Problem of Design & Test |
| 10A: Paper Session - Defect Analysis and Fault Simulation |
| 10B: Paper Session - Issues in Reliability |
| 11A: Paper Session - Wireless and System Testing |
Pei-Si Wu, National Taiwan University, Taipei
Huei Wang, National Taiwan University, Taipei pp. 347
| 11B: Paper Session - System-on-Chip Testing |
| 11C: Innovative Practices Session - The Impact of SER |
| 12A: Paper Session - Analog Testing and Design Validation |
T. Balen, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
A. Andrade Jr., Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
F. Aza?, Universit? de Montpellier II, France
M. Lubaszewski, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil; Universidad de Sevilla, Spain pp. 383
| 12B: Embedded Tutorial Session - Design for Yield |
| 12C: Innovative Practices Session - Optimizing Manufacturing Process |
How Can Design for Manufacturability Improve Mask Costs and Yields?
Collaboration through Industry Standards for Manufacturing Success
Enhancement to IEEE 1149.1 Enables Simplified Parallel Test of ICs
| 13A: Embedded Tutorial Session - Design for Manufacturability |
| 13B: Hot Topic Session - Software-based Embedded Test |
| 13C: Panel Session - Defect-based Testing and Burn-in: A Test Solution for Scaled Technology? | Usage of this product signifies your acceptance of the Terms of Use.
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