We propose a framework for designing reconfigurable multiple scan chains for systems-on-chip to minimize test application time. Multiple scan chain design problem defined in this paper involves (1) designing a suitable reconfigurable scan chain architecture, (2) partitioning wrapper cells and core internal scan registers into multiple scan chains, (3) ordering the wrapper cells and the internal scan registers within each scan chain, and (4) identifying sessions in which to activate bypass control signals. We demonstrate significant reductions in test application times and hardware costs over prior heuristics.