A wireless technique for characterization of Very Large Scale ICs and wafers is presented.Presented is a test technique that uses standard CMOS without the use of inductors to achieve wireless parametric testing. In terms of existing technologies, this system has virtually no area overhead,minimal power requirements, and no process or design changes are required. A major feature is that wafer/chip contact is not required. Presented are specific circuit simulations showing characteristics of operation under varying conditions. The circuit operation is shown to work down to 1 volt and sub-milliwatt power level at the same time as being 1/10,000{th} the area of a Pentium class VLSI circuit.