Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densities are increasing with submicron scaling, more advanced solutions may be required for memories to be produced with the upcoming nanometric CMOS process generations. This problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels that are several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents a diversified repair approach merging ECC codes and self-repair, for repairing memories affected by high defect densities. The approach was validated by means of statistical fault injection simulations considering defect densities as high as 3*10{-2} % (3% of cells are defective). The obtained results show that the approach provides close to 100% memory yield, by means of reasonable hardware cost, for technologies of very poor quality. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories.