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22nd IEEE VLSI Test Symposium
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs
Napa Valley, California
April 25-April 29
ISBN: 0-7695-2134-7
Zaid Al-Ars, Delft University of Technology, The Netherlands
Said Hamdioui, Delft University of Technology, The Netherlands
Ad J. van de Goor, Delft University of Technology, The Netherlands
With the shrinking dimensions of manufactured structures on memory chips and the increase in memory size, bit line coupling is becoming ever more influential on the memory behavior. This paper discusses the effects of bit line coupling on the faulty behavior of DRAMs. It starts with an analytical evaluation of coupling effects, followed by a simulation-based fault analysis using a Spice simulation model. Two bit line coupling mechanisms are identified, pre-sense and post-sense coupling, and found to have a partly opposing effect on the faulty behavior. In addition, the impact of neighboring cells on these coupling mechanisms is investigated.
Index Terms:
DRAMs, bit line coupling, faulty behavior, data backgrounds, Spice simulation
Citation:
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, "Effects of Bit Line Coupling on the Faulty Behavior of DRAMs," vts, pp.117, 22nd IEEE VLSI Test Symposium, 2004
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