22nd IEEE VLSI Test Symposium FPGA Bridging Fault Detection and Location via Differential I{DDQ} Napa Valley, California April 25-April 29 ISBN: 0-7695-2134-7
Standard I{DDQ} testing is limited by the ability to distinguish a small fault current from a large background leakage current: this limitation is overcome in FPGAs by differential I{DDQ} testing. Partitioning of interconnects further increases the detectability of a fault current.Fault location can be achieved by iteratively applying partitioned differential I{DDQ} testing to eliminate fault-free nets. The location algorithm, easily automated, requires very few configurations and I{DDQ} measurements, logarithmic to the number of initially-suspected faulty nets.
Citation:
Erik Chmelar, Shahin Toutounchi, "FPGA Bridging Fault Detection and Location via Differential I{DDQ}," vts, pp.109, 22nd IEEE VLSI Test Symposium, 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||