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22nd IEEE VLSI Test Symposium
Yield Analysis of Logic Circuits
Napa Valley, California
April 25-April 29
ISBN: 0-7695-2134-7
ASCII Text
x 
 
D. Appello, A. Fudoli, K. Giarda, E. Gizdarski, B. Mathew, V. Tancorre, "Yield Analysis of Logic Circuits," VLSI Test Symposium, IEEE, pp. 103, 22nd IEEE VLSI Test Symposium, 2004.
 
 
BibTex
x
 
@article{ 10.1109/VTEST.2004.1299232,
author = {D. Appello and A. Fudoli and K. Giarda and E. Gizdarski and B. Mathew and V. Tancorre},
title = {Yield Analysis of Logic Circuits},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2004},
issn = {1093-0167},
pages = {103},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299232},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Yield Analysis of Logic Circuits
SN - 1093-0167
SP
EP
A1 - D. Appello,
A1 - A. Fudoli,
A1 - K. Giarda,
A1 - E. Gizdarski,
A1 - B. Mathew,
A1 - V. Tancorre,
PY - 2004
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
D. Appello, ST Microelectronics, Cornaredo, Italy
A. Fudoli, ST Microelectronics, Cornaredo, Italy
K. Giarda, ST Microelectronics, Cornaredo, Italy
E. Gizdarski, Synopsys Inc., Mountain View, CA
B. Mathew, Synopsys Inc., Mountain View, CA
V. Tancorre, ST Microelectronics, Cornaredo, Italy
Complex SOC's developed in VDSM technologies require adequate solutions to diagnose and analyze yield losses. This paper focuses on the diagnosis of logic circuits embedded in SOCs. The core instrument leveraged is ATPG used during test vectors generation and analysis of failures. This work emphasizes the results obtained in systematically applying ATPG diagnosis on failures detected in the manufacturing test floor. Details on diagnosis flow and ATE data collection are given. Experimental results are provided.
Citation:
D. Appello, A. Fudoli, K. Giarda, E. Gizdarski, B. Mathew, V. Tancorre, "Yield Analysis of Logic Circuits," vts, pp.103, 22nd IEEE VLSI Test Symposium, 2004
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