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- VTS
- 2003
- 21st IEEE VLSI Test Symposium
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21st IEEE VLSI Test Symposium Napa Valley, California April 27-May 01 ISBN: 0-7695-1924-5 Table of Contents
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| Plenary Session |
ITTC: 25 Years of Service
TTEP 2002 Best Tutorial Award
| Session 1A: New Directions in Scan Test |
| Session 1B: Outlier Identification & Current Based Test |
C. Lu, LSI Logic Corporation pp. 39
| IP Session 1C: How to Get to Open Architecture ATE? |
Assuring Signal Integrity Exists in an Open Architecture
Scalability Challenges in Open Architecture ATE
Open Architecture Testers: The Value Proposition for User's
| Session 2A: Advances in Built-In Self-Test - I |
| Session 2B: Analog and Mixed-Signal Test - I |
Luigi Carro, Universidade Federal do Rio Grande do Sul - UFRGS pp. 77
| IP Session 2C: Silicon Proven IP Cores |
The Testing and Qualification of ARM Cores
Qualification and Test for Embedded Memory IP
Requirements and Challenges for Silicon-Proven Libraries
| Session 3A: Test Compaction |
| Session 3B: Testing Buses and On-Chip Interconnect |
E. Cota, PPGC - Inst. de Inform?tica
C.A. Zeferino, PPGC - Inst. de Inform?tica; Centro de Ci?ncias Tecnol?gicas da Terra e do Mar - Univali
L. Carro, PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
M. Lubaszewski, PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica
A. Susin, PPGC - Inst. de Inform?tica; PPGEE - Depto. Engenharia El?trica pp. 128
| IP Session 3C: Test and Diagnosis of ICs Using 130 nm & 90 nm Technologies |
Defect Screening & Failure Analysis in 90nm
Test Cost Challenges: Test Foundry Business Perspective
Solutions for 'New' Problems, for 130nm and Beyond
| Session 4A: Test Challenges in Nanometer Technologies |
N. Ahmed, The University of Texas at Dallas pp. 158
| IP Session 4C: Test Data Analysis |
Analysis of "Partial Open" Defects - Are Delay Failures More Likely with Copper Interconnects?
Facts Unmask Culprits: Process Monitoring Using Test Data
Yield Improvement through Statistical Analysis of Test Data
| Special Session 5A: Panel |
Is Open Architecture the Future of ATE?
| Special Session 5B: Panel |
Emerging Technology: Challenges in the Fabrication and Test of DNA Microarray Based Bio-chips
| Session 6A: Advanced Test Generation and Fault Simulation Techniques |
| Session 6B: Analog and Mixed-Signal Test - 2 |
| IP Session 6C: Testing High Speed I/Os |
PCI Express and Hypertransport: Examples for the Test Challenges and Solutions of Today's High-Speed IO Interfaces
A Low Cost, Accurate, I/O Test Methodology
Don't Touch Those Pins! Manufacturing Test for High Speed Serial Interfaces
| Session 7A: Test Data Compression |
| Session 7B: Memory Testing |
| IP Session 7C: ATE Facilities for Modular SoC Testing |
Potential Applications for Multi-Port ATE
Cost-Effective SoC Core-Based Yield Tracking
The Role of a DfT-Focused Tester in SoC Validation
| Session 8A: Power Consumption and Test |
Dan Zhao, State University of New York at Buffalo pp. 273
| Session 8B: Testing Core-Based SoCs |
| IP Session 8C: Layout Driven Design for Test & Manufacturability |
Design for Yield and Manufacturability through Integrated Yield Optimization
Layout Driven TAM and Scan Chain Optimization
Modeling Yield Improvement Objectives in Compaction Tools
| Special Session 9A: Panel |
Future Vision for ATE Software
| Special Session 9B: Panel |
Embedded Tutorial: Yield & Repair Analysis
| Special Session 9C: Panel |
| Session 10A: System-Level Test Issues |
Erik Larsson, Linkopings Universitet; Nara Institute of Science and Technology pp. 319
| Session 10B: Diagnosis Techniques |
Li-C. Wang, University of California, Santa Barbara pp. 339
| Session 11A: Advances in Built-In Self-Test - 2 |
| Session 11B: Test in the Presence of Bridging Faults |
Lei Wang, University of Southern California pp. 385
| IP Session 11C: SoC Test Practices for Consumer Products |
Test Point Insertion Methods to Reduce Test Application Time for SoCs
Design and Test of a SoC Design with Built-In Redundancy Allocation of SRAMs
A Practical Design of At-Speed Logic BIST for Large SoCs
| Session 12A: Emerging Circuit Technologies: Test Challenges |
| IP Session 12C: P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data |
Using DFT Disclosure Information for Economic Merging of Soft Cores
Generic Programmable Memory BIST for Testing Custom Embedded Memories in High Performance Microprocessors
A Case Study in Test Integration of Soft Cores in a Complex SoC Design Using DFT Disclosure Document
| Special Session 13A: Panel |
Hot Topic: ITRS Roadmap 2003
| Special Session 13B: Panel |
Designing with Unreliable Components
| Special Session 13C: Panel |
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