Design for Self-Checking and Self-Timed Datapath

V
VTS
2003
21st IEEE VLSI Test Symposium
Abstract - Design for Self-Checking and Self-Timed Datapath

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21st IEEE VLSI Test Symposium

Napa Valley, California

April 27-May 01

ISBN: 0-7695-1924-5

	ASCII Text	x
	Jing-ling Yang, Chiu-sing Choy, Cheong-fat Chan, Kong-pong Pun, "Design for Self-Checking and Self-Timed Datapath," VLSI Test Symposium, IEEE, pp. 417, 21st IEEE VLSI Test Symposium, 2003.

	BibTex	x
	@article{ 10.1109/VTEST.2003.1197683, author = {Jing-ling Yang and Chiu-sing Choy and Cheong-fat Chan and Kong-pong Pun}, title = {Design for Self-Checking and Self-Timed Datapath}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2003}, issn = {1093-0167}, pages = {417}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197683}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Design for Self-Checking and Self-Timed Datapath SN - 1093-0167 SP EP A1 - Jing-ling Yang, A1 - Chiu-sing Choy, A1 - Cheong-fat Chan, A1 - Kong-pong Pun, PY - 2003 KW - Self-checking KW - asynchronous datapath KW - differential cascode voltage switch logic KW - dynamic circuits VL - 0 JA - VLSI Test Symposium, IEEE ER -

Jing-ling Yang, The University of Hong Kong

Chiu-sing Choy, The Chinese University of Hong Kong

Cheong-fat Chan, The Chinese University of Hong Kong

Kong-pong Pun, The Chinese University of Hong Kong

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197683

This work examines the inherent self-checking property of a latch-free dynamic asynchronous Datapath (LFDAD) using differential cascode voltage switch logic (DCVSL).

Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

Index Terms:

Self-checking, asynchronous datapath, differential cascode voltage switch logic, dynamic circuits

Citation:

Jing-ling Yang, Chiu-sing Choy, Cheong-fat Chan, Kong-pong Pun, "Design for Self-Checking and Self-Timed Datapath," vts, pp.417, 21st IEEE VLSI Test Symposium, 2003

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