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21st IEEE VLSI Test Symposium
Testable Design and Testing of Micro-Electro-Fluidic Arrays
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
ASCII Text
x 
 
Hans G. Kerkhoff, Mustafa Acar, "Testable Design and Testing of Micro-Electro-Fluidic Arrays," VLSI Test Symposium, IEEE, pp. 403, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197681,
author = {Hans G. Kerkhoff and Mustafa Acar},
title = {Testable Design and Testing of Micro-Electro-Fluidic Arrays},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {403},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197681},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Testable Design and Testing of Micro-Electro-Fluidic Arrays
SN - 1093-0167
SP
EP
A1 - Hans G. Kerkhoff,
A1 - Mustafa Acar,
PY - 2003
KW - Multi-domain testing
KW - MEMS testing
KW - Microsystem testing
KW - Multi-domain fault modeling & simulation
KW - Design-for-Testability
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Hans G. Kerkhoff, MESA+ Research Institute
Mustafa Acar, MESA+ Research Institute
The testable design and testing of a fully software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is presented. Test hardware is included for detecting faults in the DMOS electro-fluidic interface and the digital parts. Multi-domain fault modeling and simulation shows the effects of faults in the (combined) fluidic and electrical parts. The fault simulations also reveal important parameters of multi-domain test-stimuli, e.g. fluid velocity, for detecting both electrical and fluidic defects.
Index Terms:
Multi-domain testing, MEMS testing, Microsystem testing, Multi-domain fault modeling & simulation, Design-for-Testability
Citation:
Hans G. Kerkhoff, Mustafa Acar, "Testable Design and Testing of Micro-Electro-Fluidic Arrays," vts, pp.403, 21st IEEE VLSI Test Symposium, 2003
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