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21st IEEE VLSI Test Symposium
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
ASCII Text
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Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz, "Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation," VLSI Test Symposium, IEEE, pp. 351, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197674,
author = {Xiaoming Yu and M. Enamul Amyeen and Srikanth Venkataraman and Ruifeng Guo and Irith Pomeranz},
title = {Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {351},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197674},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation
SN - 1093-0167
SP
EP
A1 - Xiaoming Yu,
A1 - M. Enamul Amyeen,
A1 - Srikanth Venkataraman,
A1 - Ruifeng Guo,
A1 - Irith Pomeranz,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Xiaoming Yu, Intel Corporation
M. Enamul Amyeen, Purdue University
Srikanth Venkataraman, Intel Corporation
Ruifeng Guo, Intel Corporation
Irith Pomeranz, Purdue University
Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator and an equivalence identification tool. Diagnostic fault simulation can be an expensive process for large circuits. If a large number of fault pairs are passed to an equivalence identification tool, it would take a long time. In this paper, a novel approach is proposed to concurrently execute diagnostic fault simulation and equivalence identification during diagnostic test generation, thereby reducing the overall execution time. Experimental results on industrial circuits and benchmark circuits demonstrate the potential of the proposed method.
Citation:
Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz, "Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation," vts, pp.351, 21st IEEE VLSI Test Symposium, 2003
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