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21st IEEE VLSI Test Symposium
Layered Approach to Designing System Test Interfaces
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
ASCII Text
x 
 
Man Wah Chiang, Zeljko Zilic, "Layered Approach to Designing System Test Interfaces," VLSI Test Symposium, IEEE, pp. 331, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197671,
author = {Man Wah Chiang and Zeljko Zilic},
title = {Layered Approach to Designing System Test Interfaces},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {331},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197671},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Layered Approach to Designing System Test Interfaces
SN - 1093-0167
SP
EP
A1 - Man Wah Chiang,
A1 - Zeljko Zilic,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Man Wah Chiang, McGill University
Zeljko Zilic, McGill University
The layered system design approach has shown its strength in the design of the network and other complex systems. In this paper, we apply this approach to the design of system testing interfaces. The system is partitioned into layers to maximize reuse, and ease the development. In this paper, we demonstrate this methodology by designing a low-overhead testing interface and circuitry for the Infiniband Architecture (IBA).
Citation:
Man Wah Chiang, Zeljko Zilic, "Layered Approach to Designing System Test Interfaces," vts, pp.331, 21st IEEE VLSI Test Symposium, 2003
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