loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
21st IEEE VLSI Test Symposium
Power Constrained Test Scheduling with Dynamically Varied TAM
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
Dan Zhao, State University of New York at Buffalo
Shambhu Upadhyaya, State University of New York at Buffalo
In this paper, we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level TAM constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30% of SoC testing time reduction can be achieved by using our scheduling approach.
Citation:
Dan Zhao, Shambhu Upadhyaya, "Power Constrained Test Scheduling with Dynamically Varied TAM," vts, pp.273, 21st IEEE VLSI Test Symposium, 2003
Usage of this product signifies your acceptance of the Terms of Use.