A new software-based test vector compression technique is proposed for using an embedded processor to test the other components of a system-on-a-chip (SOC). The tester transfers compressed test data to the processor?s on-chip memory, and the processor executes a small program which decompresses the data and applies it to the scan chains of each core-under-test. The proposed decompression procedure uses word-based linear operations to expand the compressed test data into the corresponding deterministic test vectors. It has a number of nice features that overcome the drawbacks of software-based linear feedback shift register (LFSR) reseeding. The storage requirements for the proposed approach depend only on the total number of specified bits in the test set. There are no restrictions on static compaction or the test generation procedure as a whole. The decompression program can be easily reused for applying different test sets. Experimental results demonstrate that the proposed approach compares very favorably with all previously published results for software-based test vector decompression.