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21st IEEE VLSI Test Symposium
Automatic Configuration Generation for FPGA Interconnect Testing
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
ASCII Text
x 
 
Mehdi Baradaran Tahoori, Subhasish Mitra, "Automatic Configuration Generation for FPGA Interconnect Testing," VLSI Test Symposium, IEEE, pp. 134, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197644,
author = {Mehdi Baradaran Tahoori and Subhasish Mitra},
title = {Automatic Configuration Generation for FPGA Interconnect Testing},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {134},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197644},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Automatic Configuration Generation for FPGA Interconnect Testing
SN - 1093-0167
SP
EP
A1 - Mehdi Baradaran Tahoori,
A1 - Subhasish Mitra,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Mehdi Baradaran Tahoori, Stanford University, CA
Subhasish Mitra, Intel Corporation
We present a new automatic test configuration generation technique for manufacturing testing of interconnect network of SRAM-based FPGA architectures. The technique guarantees detection of open and bridging faults in all wiring channels and programmable switches in the interconnects. Only 8 test configurations are required to achieve 100% coverage of stuck-open, stuck-closed, open and bridging faults in the interconnects of Xilinx Virtex FPGAs.
Citation:
Mehdi Baradaran Tahoori, Subhasish Mitra, "Automatic Configuration Generation for FPGA Interconnect Testing," vts, pp.134, 21st IEEE VLSI Test Symposium, 2003
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