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21st IEEE VLSI Test Symposium
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
ASCII Text
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Ismet Bayraktaroglu, Alex Orailoglu, "Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression," VLSI Test Symposium, IEEE, pp. 113, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197641,
author = {Ismet Bayraktaroglu and Alex Orailoglu},
title = {Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {113},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197641},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression
SN - 1093-0167
SP
EP
A1 - Ismet Bayraktaroglu,
A1 - Alex Orailoglu,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Ismet Bayraktaroglu, Sun Microsystems
Alex Orailoglu, University of California, San Diego
A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed. Test cube information is utilized for the determination of a near optimal decompression hardware. The proposed scheme attains simultaneously high compression levels and reduced pattern counts through a linear decompression hardware. Significant test volume and test application time reductions are delivered through the scheme we propose while a highly cost effective hardware implementation is retained.
Citation:
Ismet Bayraktaroglu, Alex Orailoglu, "Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression," vts, pp.113, 21st IEEE VLSI Test Symposium, 2003
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