Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal signals are observed through a small number of output pins or into a small signature analyzer, requiring a combinational space compactor. This paper analyzes the basic requirements of compactors to support efficient test and diagnosis, focusing on practical compactors where all inputs have fanout two. We show how graph theory can be used to model compactors and design compactors with robust non-aliasing properties that have minimal area and delay overhead and are independent of the test set, the fault model and the circuit tested.