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21st IEEE VLSI Test Symposium
High Speed Ring Generators and Compactors of Test Data
Napa Valley, California
April 27-May 01
ISBN: 0-7695-1924-5
ASCII Text
x 
 
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, "High Speed Ring Generators and Compactors of Test Data," VLSI Test Symposium, IEEE, pp. 57, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197633,
author = {Grzegorz Mrugalski and Janusz Rajski and Jerzy Tyszer},
title = {High Speed Ring Generators and Compactors of Test Data},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {57},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197633},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - High Speed Ring Generators and Compactors of Test Data
SN - 1093-0167
SP
EP
A1 - Grzegorz Mrugalski,
A1 - Janusz Rajski,
A1 - Jerzy Tyszer,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Grzegorz Mrugalski, Poznan University of Technology
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznan University of Technology
The paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial.
Citation:
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, "High Speed Ring Generators and Compactors of Test Data," vts, pp.57, 21st IEEE VLSI Test Symposium, 2003
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