Foreword

VTS 20th Anniversary Page (PDF)

pp. xvii

Acknowledgements (PDF)

pp. xviii

Organizing Committee (PDF)

pp. xix

Steering Committee (PDF)

pp. xxii

Program Committee (PDF)

pp. xxiii

Reviewers (PDF)

pp. xxiv

Test Technology Technical Council (PDF)

pp. xxvii

Test Technology Educational Program: Overview of Tutorials (PDF)

pp. xxx

Welcome Message: Joan Figueras, General Chair

Keynote Address (PDF)

Michael Hackworth, Cirrus Logic, Inc.

pp. xxxv

Plenary Address: Business and Technical Challenges for Testing the Ghz Age (PDF)

Program Introduction: Andre Ivanov, Program Chair

Jai K. Hakhu, Intel Corporation

pp. xxxvii

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture (Abstract)

Session 1: Microprocessor Test: Moderators: M. d'Abreau, Ample Communications

Nandu Tendolkar, Motorola, Inc.

Rajesh Raina, Motorola, Inc.

Rick Woltenberg, Motorola, Inc.

Xijiang Lin, Mentor Graphics Corporation

Bruce Swanson, Mentor Graphics Corporation

Greg Aldrich, Mentor Graphics Corporation

pp. 0003

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Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs (Abstract)

Amit R. Pandey, University of Illinois at Urbana-Champaign

Tanak H. Patel, University of Illinois at Urbana-Champaign

pp. 0009

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Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor (Abstract)

Dilip K. Bhavsar, Intel Corporation

Richard A. Davies, Compaq Computer Corporation

pp. 0016

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Session 2: Applications of Very Low Voltage and Slow Speed Testing: Moderators: K. Eshraghian, Edith Cowan University

Very Low Voltage Testing of SOI Integrated Circuits (Abstract)

Eric MacDonald, IBM Microelectronics Division

Nur A. Touba, University of Texas at Austin

pp. 0025

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Performance Comparison of VLV, ULV, and ECR Tests (Abstract)

Wanli Jiang, Guidant Corporation

Eric Peterson, Guidant Corporation

pp. 0031

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Experimental Results for Slow-Speed Testing (Abstract)

Chao-Wen Tseng, Stanford University

James Li, Stanford University

Edward J. McCluskey, Stanford University

pp. 0037

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IP Session 1: Innovations in Test Automation

Innovations in Test Automation (PDF)

J. Borel

Anand Raghunathan, NEC

Jim Sproch, Synopsys Inc.

Michael Howells, Logic Vision Inc.

Janusz Rajski, Mentor Graphics Corp.

pp. 0043

Session 3: Advancements in Scan-Based Testing: Moderators: M. Lousberg, Philips

Scan-Path with Directly Duplicated and Inverted Duplicated Registers (Abstract)

M. Goessel, University of Potsdam

E. Sogomonyan, University of Potsdam

A. Singh, Auburn University

pp. 0047

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An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits (Abstract)

Aiman El-Maleh, King Fahd University of Petroleum and Minerals

Ali Al-Suwaiyan, King Fahd University of Petroleum and Minerals

pp. 0053

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Logic BIST and Scan Test Techniques for Multiple Identical Blocks (Abstract)

Karim Arabi, PMC Sierra,Inc.

pp. 0060

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Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies (Abstract)

Session 4: Burn-in Reduction or Alternatives: Moderators: K. Mandl, Teradyne

Robert Madge, LSI Logic Corporation

Manu Rehani, LSI Logic Corporation

Kevin Cota, LSI Logic Corporation

W. Robert Daasch, Portland State University

pp. 0069

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Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction (Abstract)

Thomas S. Barnett, Auburn University

Adit D. Singh, Auburn University

Matt Grady, IBM Microelectronics

Kathleen Purdy, IBM Microelectronics

pp. 0075

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Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction (Abstract)

Sagar S. Sabade, Texas A&M University

Duncan M. Walker, Texas A&M University

pp. 0081

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A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required? (PDF)

IP Session 2: DFT Testers 1

Lee Song, Teradyne

Rudy Garcia, Schlumberger

Andrew Levy, Teseda

Don Wheater, IBM

pp. 0087

Session 5: Test Set Compression Techniques: Moderators: K. Butler, Texas Instruments

How Effective are Compression Codes for Reducing Test Data Volume? (Abstract)

Anshuman Chandra, Duke University

Krishnendu Chakrabarty, Duke University

Rafael A. Medina, Massachusetts Institute of Technology

pp. 0091

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Test Vector Compression Using EDA-ATE Synergies (Abstract)

Ajay Khoche, Agilent Technologies, Inc.

Erik Volkerink, Agilent Technologies, Inc.

Jochen Rivoir, Agilent Technologies, Inc.

Subhasish Mitra, Intel Corporation

pp. 0097

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On Test Data Volume Reduction for Multiple Scan Chain Designs (Abstract)

Sudhakar M. Reddy, University of Iowa

Kohei Miyase, Kyushu Institute of Technology

Seiji Kajihara, Kyushu Institute of Technology

Irith Pomeranz, Purdue University

pp. 0103

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Session 6: Analog BIST: Moderators: J. da Franca, ChipIdea

Spectrum-Based BIST in Complex SOCs (PDF)

Ganapathy Kasturirangan, Intel Corporation

Michael S. Hsiao, Virginia Tech

pp. 0111

A Self Calibrated ADC BIST Methodology (Abstract)

Hung-kai Chen, Nation Central University

Chih-hu Wang, Nation Central University

Chau-chin Su, Nation Central University

pp. 0117

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Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus (Abstract)

Chee-Kian Ong, University of California at Santa Barbara

Kwang-Ting (Tim) Cheng, University of California at Santa Barbara

pp. 0123

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A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution? (PDF)

IP Session 3: DFT Testers 2

B. Bottoms, 3MTS

Lee Song, Teradyne

Paul Patton, Advantest

Wilhelm Radermacher, Agilent Technologies

pp. 0129

Session 7: Increased Efficiency Testing: Moderators: B. Pouya, Banderacom

Testing High-Speed SoCs Using Low-Speed ATEs (Abstract)

Mehrdad Nourani, University of Texas at Dallas

James Chin, Texas Instruments,Inc.

pp. 0133

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Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs (Abstract)

Madhu K. Iyer, University of California at Santa Barbara

Kwang-Ting Cheng, University of California at Santa Barbara

pp. 0139

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On Using Efficient Test Sequences for BIST (Abstract)

R. David, Laboratoire d ?Automatique de Grenoble

P. Girard, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

C. Landrault, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

S. Pravossoudovitch, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

A. Virazel, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

pp. 0145

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Session 8: Controlling and Reducing Test Power: Moderators: A. Crouch, Inovys

Controlling Peak Power During Scan Testing (Abstract)

Ranganathan Sankaralingam, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 0153

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Test Vector Modification for Power Reduction during Scan Testing (Abstract)

Seiji Kajihara, Kyushu Institute of Technology

Koji Ishida, Kyushu Institute of Technology

Kohei Miyase, Kyushu Institute of Technology

pp. 0160

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Test Power Reduction through Minimization of Scan Chain Transitions (Abstract)

Ozgur Sinanoglu, University of California at San Diego

Ismet Bayraktaroglu, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 0166

PDF

IP Session 4

Wireless Test (PDF)

Robert Aitken, Agilent Technologies

Mustapha Slamani, IBM Microelectronics

H. Ding, IBM Microelectronics

William R. Eisenstadt, University of Florida

Sanghoon Choi, University of Florida

John McLaughlin, Agilent Technologies

pp. 0173

Special Session 1: Panel

Analog and Mixed Signal BIST: Too Much, Too Little, Too Late? (PDF)

Adam Osseiran, IMS

William De Wilkins, National Semiconductor

Barry Baril, Credence

Sassan Tabatabaei, Vector 12

Fidel Muradali, Agilent Technologies

Ken Posse, Teseda

Lee Song, Teradyne

pp. 0175

Special Session 2: Panel

Test as a Key Enabler for Faster Yield Ramp-Up (PDF)

Julie Segal, HPL Technology

Rene Segers, Philips

R. Aitke, Agilent Technologies

S. Eichenberge, Philips

A. Gattike, IBM

M. Millegen, HPL Technology

R. Seger, Philips

S. Venkataraman, Intel

pp. 0177

Session 9: Diagnosis: Moderators: F. Maamari, LogicVision

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits (Abstract)

M. Enamul Amyeen, Purdue University

Irith Pomeranz, Purdue University

W. Kent Fuchs, Purdue University

pp. 0181

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Diagnosis of Sequence-Dependent Chips (Abstract)

James C.-M. Li, Stanford University

E. J. McCluskey, Stanford University

pp. 0187

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Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation (Abstract)

Shi-Yu Huang, National Tsing-Hua University

pp. 0193

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Session 10: Analog Circuit Testing: Moderators: J. Abraham, University of Texas at Austin

Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus (Abstract)

Jose Vicente Calvano, Brazilian Navy Research Institute

Vladimir Castro Alves, Federal University of Rio de Janeiro

Antonio C. Mesquita, Federal University of Rio de Janeiro

Marcelo Lubaszewski, Federal University of Rio Grande do Su

pp. 0201

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Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division (Abstract)

Takahiro J. Yamaguchi, Advantest Laboratories, Ltd.

Masahiro Ishida, Advantest Laboratories, Ltd.

Mani Soma, University of Washington

Louis Malarsie, Agere Systems

Hirobumi Musha, Advantest Corporation

pp. 0207

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Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis (Abstract)

Sule Ozev, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 0213

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Session 11: High Level Test Techniques: Moderators: J. Aylor, Virginia Tech

Instruction-Based Self-Testing of Processor Cores (Abstract)

N. Kranitis, University of Athens

A. Paschalis, University of Athens

D. Gizopoulos, University of Piraeus

Y. Zorian, LogicVision

pp. 0223

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An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation (Abstract)

Luis Berrojo, Alcatel Espacio, S.A.

Isabel González, Alcatel Espacio, S.A.

Fulvio Corno, Politecnico di Torino

Matteo Sonza-Reorda, Politecnico di Torino

Giovanni Squillero, Politecnico di Torino

Luis Entrena, Universitad Carlos III

Celia Lopez, Universitad Carlos III

pp. 0229

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Program Slicing for Hierarchical Test Generation (Abstract)

Vivekananda M. Vedula, University of Texas at Austin

Jacob A. Abraham, University of Texas at Austin

Jayanta Bhadra, Motorola Inc.

pp. 0237

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Session 12: SoC Test Infrastructure: Moderators: M. Mowji, LogicVision

Design for Testability and Testing of IEEE 1149.1 Tap Controller (Abstract)

Subhasish Mitra, Intel Corporation

Edward J. McCluskey, Stanford University

Samy Makar, Transmeta Corporation

pp. 0247

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On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization (Abstract)

Vikram Iyengar, Duke University

Krishnendu Chakrabarty, Duke University

Erik Jan Marinissen, Philips Research Laboratories

pp. 0253

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Cluster-Based Test Architecture Design for System-on-Chip (Abstract)

Sandeep Kumar Goel, Philips Research Laboratories

Erik Jan Marinissen, Philips Research Laboratories

pp. 0259

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IP Session 5: Multi-GigaHertz Testing Challenges and Solutions

Multi-GigaHertz Testing Challenges and Solutions (PDF)

Karim Arabi, PMC Sierra

Klaus-Dieter Hilliges, Agilent Technologies

David Keezer, Georgia Institute of Technology

Sassan Tabatabaei, Vector 12

pp. 0265

Session 13: Test Tools and Algorithms: Moderators: T. Williams, Synopsys

Exploiting Dominance and Equivalence using Fault Tuples (Abstract)

Kumar N. Dwarakanat, Carnegie Mellon University

R. D. (Shawn) Blanton, Carnegie Mellon University

pp. 0269

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Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? (Abstract)

Narayanan Krishnamurthy, Motorola

Jayanta Bhadra, Motorola

Magdy S. Abadir, Motorola

Jacob A. Abraham, University of Texas at Austin

pp. 0275

PDF

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics (Abstract)

Kuo-Liang Cheng, National Tsing Hua University

Jen-Chieh Yeh, National Tsing Hua University

Chih-Wea Wang, National Tsing Hua University

Chih-Tsun Huang, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 0281

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Session 14: Supply Current Testing: Moderators: T. Storey, PDF

Eigen-Signatures for Regularity-based IDDQ Testing (Abstract)

Yukio Okuda, Sony Corporation

pp. 0289

PDF

Speeding-Up IDDQ Measurements (Abstract)

C. Thibeault, ?cole de Technologie Sup?rieure

pp. 0295

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Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform (Abstract)

Swarup Bhunia, Purdue University

Kaushik Roy, Purdue University

pp. 0302

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Special Session 3: Panel

Debating the Future of Burn-In (PDF)

Edward J. McCluske, Stanford University

Subhasish Mitra, Agilent Technologies

Bob Madge, LSI Logic

Peter Maxwell, Agilent Technologies

Phil Nigh, IBM

Mike Rodgers, Intel Corporation

pp. 0311

Special Session 4: Hot Topic

Beyond CMOS (PDF)

B. Courtoi, TIMA

M. Forshaw, University College, London

pp. 0315

Special Session 5: Embedded Tutorial

Challenges of Mixed-Signal Board Design and Test (PDF)

G. Roberts, McGill University

pp. 0317

Session 15: Test Pattern Generation: Moderators: J. Hayes, University of Michigan

A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits (Abstract)

Satoshi Ohtake, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

Shunjiro Miwa, NEC Corporation

pp. 0321

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A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits (Abstract)

Toshinori Hosokawa, Semiconductor Technology Academic Research Center

Hiroshi Date, Semiconductor Technology Academic Research Center

Michiaki Muraoka, Semiconductor Technology Academic Research Center

pp. 0328

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Test Pattern Generation for Signal Integrity Faults on Long Interconnects (Abstract)

Amir Attarha, LSI Logic, Corporation

Mehrdad Nourani, University of Texas at Dallas

pp. 0336

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Session 16: Tester Hardware Modeling and Improvements: Moderators: M. Topsakal, Cypress

Improved Test Monitor Circuit in Power Pin DfT (Abstract)

Rodger Schuttert, Philips Research

Frans de Jong, Philips Research

Ben Kup, Philips Consumer Electronics

pp. 0345

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Measuring Stray Capacitance on Tester Hardware (Abstract)

Achintya Halder, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

Pramod Variyam, Texas Instruments Inc.

John Ridley, Texas Instruments Inc.

pp. 0351

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Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models (Abstract)

Abhishek Singh, University of Maryland at Baltimore County

Jim Plusquellic, University of Maryland at Baltimore County

Anne Gattiker, IBM Austin Research Labs

pp. 0357

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Session 17: Fault Modeling & Extraction: Moderators: G. Robinson, 3MTS

Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms (Abstract)

Sreejit Chakravarty, Intel Corporation

Kambiz Komeyli, Intel Corporation

Eric W. Savage, Intel Corporation

Michael J. Carruthers, Intel Corporation

Bret T. Stastny, Intel Corporation

Sujit T. Zachariah, Intel Corporation

pp. 0367

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Fault Models for Speed Failures Caused by Bridges and Opens (Abstract)

Sreejit Chakravarty, Intel Corporation

Ankur Jain, Intel Corporation

pp. 0373

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Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits (Abstract)

Rahul Kundu, Carnegie Mellon University

R. D. (Shawn) Blanton, Carnegie Mellon University

pp. 0379

PDF

Session 18: Memory Testing: Moderators: N. Saxena, Chip Engines

Testing and Diagnosing Embedded Content Addressable Memories (Abstract)

Jin-Fu Li, National Tsing Hua University

Ruey-Shing Tzeng, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 0389

PDF

Testing Static and Dynamic Faults in Random Access Memories (Abstract)

Said Hamdioui, Intel Corporation and Delft University of Technology

Zaid Al-Ars, Delft University of Technology

Ad J. van de Goor, Delft University of Technology

pp. 0395

PDF

Approximating Infinite Dynamic Behavior for DRAM Cell Defects (Abstract)

Zaid Al-Ars, Delft University of Technology

Ad J. van de Goor, Delft University of Technology

pp. 0401

PDF

IP Session 8

Validation and Test of Network Processors and ASICs (PDF)

C.-H. Chia, Lucent

Sujit Dey, University of California at San Diego

Faraydon Karim, ST Microelectronics

Haluk Konuk, Broadcom

Keesup Kim, Intel

pp. 0407

Session 19: Test-Cost Reduction: Moderators: D. Edenfeld, Intel

Test Economics for Multi-site Test with Modern Cost Reduction Techniques (Abstract)

Erik H. Volkerink, Agilent Laboratories

Ajay Khoche, Agilent Laboratories

Jochen Rivoir, Agilent Laboratories

Klaus D. Hilliges, Agilent Laboratories

pp. 0411

PDF

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects (Abstract)

Krishna Sekar, University of California at San Diego

Sujit Dey, University of California at San Diego

pp. 0417

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Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions (Abstract)

Paul T. Gonciari, University of Southampton

Bashir M. Al-Hashimi, University of Southampton

Nicola Nicolici, McMaster University

pp. 0423

PDF

Session 20: Oscillation - Based Test: Moderators: B. Kaminska, IMS

Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation (Abstract)

Diego Vázquez, Universidad de Sevilla

Gloria Huertas, Universidad de Sevilla

Gildas Leger, Universidad de Sevilla

Adoración Rueda, Universidad de Sevilla

José L. Huertas, Universidad de Sevilla

pp. 0433

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Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems (Abstract)

V. Beroulle, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

Y. Bertrand, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

L. Latorre, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

P. Nouet, Laboratoire d ?Informatique de Robotique et de Micro?lectronique de Montpellier

pp. 0439

PDF

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? (PDF)

Special Session 6: Panel

Fidel Muradali, Agilent Technologies

Mike Ricchetti, Intellitech

Bart Vermeulen, Philips

Bulent Dervisoglu, Cadence

Bob Gottlieb, Intel Corporation

Bernd Koenemann, IBM

C. J. Clark, Intellitech

pp. 0445

Special Session 7: Embedded Tutorial

Challenges in Nanometric Technology Scaling: Trends and Projections (PDF)

Jaume Segura, University of Illes Balears

Vivek De, Intel Corporation

Ali Keshavarzi, Intel Corporation

pp. 0447

Special Session 8: Panel

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? (PDF)

S. Mir, IMAG

H. Bederr, Motorola

R. D. Blanton, Carnegie-Mellon University

H. Kerkhoff, MESA Institute

H. J. Klim, ETEC Inc.

pp. 0449

Author Index (PDF)

pp. 0451