20th IEEE VLSI Test Symposium Test Economics for Multi-site Test with Modern Cost Reduction Techniques Monterey, California April 28-May 02 ISBN: 0-7695-1570-3
Test approaches that can be combined with multi-site, like reduced pin-count test, low channel cost ATE, and bandwidth matching, are becoming pervasive. Yet their economic benefits, the tradeoffs, and the long-term scalability of their benefits during technology progress, are not well understood. In this paper the benefits and tradeoffs will be analyzed using technical cost modeling. The dependency of the benefits on the application will be analyzed by modeling the test cost for 4 different applications. It will be shown that the mentioned test approaches can result in a significant and scalable reduction of the Cost of Test.
Citation:
Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges, "Test Economics for Multi-site Test with Modern Cost Reduction Techniques," vts, pp.0411, 20th IEEE VLSI Test Symposium, 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||