As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated with in the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved w thout significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.