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20th IEEE VLSI Test Symposium
Measuring Stray Capacitance on Tester Hardware
Monterey, California
April 28-May 02
ISBN: 0-7695-1570-3
Achintya Halder, Georgia Institute of Technology
Abhijit Chatterjee, Georgia Institute of Technology
Pramod Variyam, Texas Instruments Inc.
John Ridley, Texas Instruments Inc.
Parasitic capacitance in test hardware can affect the performance of a test and lead to poor fault coverage and/or yield loss. In an ATE setup, characterizing the stray capacitance using external instruments is difficult for practical reasons. In this paper, we present a single probe technique that uses available tester resources to measure stray capacitance of test hardware with high accuracy and precision. The proposed method uses a time measurement sub-system and a current source of the ATE for measuring stray capacitance from their charging and discharging characteristics. This capacitance measurement technique is also used to detect and diagnose faults in different tester hardware components. Measurement results and case studies on the application of this technique are presented.
Citation:
Achintya Halder, Abhijit Chatterjee, Pramod Variyam, John Ridley, "Measuring Stray Capacitance on Tester Hardware," vts, pp.0351, 20th IEEE VLSI Test Symposium, 2002
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