loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
20th IEEE VLSI Test Symposium
Improved Test Monitor Circuit in Power Pin DfT
Monterey, California
April 28-May 02
ISBN: 0-7695-1570-3
ASCII Text
x 
 
Rodger Schuttert, Frans de Jong, Ben Kup, "Improved Test Monitor Circuit in Power Pin DfT," VLSI Test Symposium, IEEE, pp. 0345, 20th IEEE VLSI Test Symposium, 2002.
 
 
BibTex
x
 
@article{ 10.1109/VTS.2002.1011163,
author = {Rodger Schuttert and Frans de Jong and Ben Kup},
title = {Improved Test Monitor Circuit in Power Pin DfT},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2002},
isbn = {0-7695-1570-3},
pages = {0345},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011163},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Improved Test Monitor Circuit in Power Pin DfT
SN - 0-7695-1570-3
SP
EP
A1 - Rodger Schuttert,
A1 - Frans de Jong,
A1 - Ben Kup,
PY - 2002
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Rodger Schuttert, Philips Research
Frans de Jong, Philips Research
Ben Kup, Philips Consumer Electronics
The power pin monitor cell developed by Philips was a significant step in solving the problem of detecting open power pins in paralleled power pin IC designs. This paper present an improved monitor cell design that provides better detection and it is further enhanced by the addition of an improved boundary scan control mechanism. Extensive trials confirm the cell performance and the presented results are analyzed and discussed. The cells were observed and controlled using an IEEE std 1149.1 TAP controller.
Citation:
Rodger Schuttert, Frans de Jong, Ben Kup, "Improved Test Monitor Circuit in Power Pin DfT," vts, pp.0345, 20th IEEE VLSI Test Symposium, 2002
Usage of this product signifies your acceptance of the Terms of Use.