A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits

V
VTS
2002
20th IEEE VLSI Test Symposium
Abstract - A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits

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20th IEEE VLSI Test Symposium

Monterey, California

April 28-May 02

ISBN: 0-7695-1570-3

	ASCII Text	x
	Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, "A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits," VLSI Test Symposium, IEEE, pp. 0328, 20th IEEE VLSI Test Symposium, 2002.

	BibTex	x
	@article{ 10.1109/VTS.2002.1011161, author = {Toshinori Hosokawa and Hiroshi Date and Michiaki Muraoka}, title = {A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2002}, isbn = {0-7695-1570-3}, pages = {0328}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011161}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits SN - 0-7695-1570-3 SP EP A1 - Toshinori Hosokawa, A1 - Hiroshi Date, A1 - Michiaki Muraoka, PY - 2002 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Toshinori Hosokawa, Semiconductor Technology Academic Research Center

Hiroshi Date, Semiconductor Technology Academic Research Center

Michiaki Muraoka, Semiconductor Technology Academic Research Center

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011161

This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.

Citation:

Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, "A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits," vts, pp.0328, 20th IEEE VLSI Test Symposium, 2002

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