A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits

V
VTS
2002
20th IEEE VLSI Test Symposium
Abstract - A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Satoshi Ohtake Articles by Hideo Fujiwara Articles by Shunjiro Miwa

20th IEEE VLSI Test Symposium

Monterey, California

April 28-May 02

ISBN: 0-7695-1570-3

	ASCII Text	x
	Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa, "A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits," VLSI Test Symposium, IEEE, pp. 0321, 20th IEEE VLSI Test Symposium, 2002.

	BibTex	x
	@article{ 10.1109/VTS.2002.1011160, author = {Satoshi Ohtake and Hideo Fujiwara and Shunjiro Miwa}, title = {A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2002}, isbn = {0-7695-1570-3}, pages = {0321}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011160}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits SN - 0-7695-1570-3 SP EP A1 - Satoshi Ohtake, A1 - Hideo Fujiwara, A1 - Shunjiro Miwa, PY - 2002 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Satoshi Ohtake, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

Shunjiro Miwa, NEC Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011160

This paper shows that path delay fault test generation problem for sequential circuits with balanced structure can be educed to segment delay fault test generation problem for their combinationally transformed circuits. We also propose a test generation method and a partially enhanced scan design method for path delay fault.

Citation:

Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa, "A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits," vts, pp.0321, 20th IEEE VLSI Test Symposium, 2002

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.