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20th IEEE VLSI Test Symposium
Exploiting Dominance and Equivalence using Fault Tuples
Monterey, California
April 28-May 02
ISBN: 0-7695-1570-3
Kumar N. Dwarakanat, Carnegie Mellon University
R. D. (Shawn) Blanton, Carnegie Mellon University
Local dominance and equivalence relationships for a single fault type have been exploited to reduce test set size and test generation time. However, these relationships have not been explored for multiple fault types. Using fault tuples, we describe how local dominance and equivalence relationships across various fault types can be derived. We also describe how the derived relationships can be used to order the faults efficiently for test generation in order to reduce test set size. Initial results using our ordered fault lists for ISCAS85 and ITC99 benchmark circuits reveals that test set size can be reduced by as much as 19%.
Citation:
Kumar N. Dwarakanat, R. D. (Shawn) Blanton, "Exploiting Dominance and Equivalence using Fault Tuples," vts, pp.0269, 20th IEEE VLSI Test Symposium, 2002
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