Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division

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20th IEEE VLSI Test Symposium

Monterey, California

April 28-May 02

ISBN: 0-7695-1570-3

	ASCII Text	x
	Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha, "Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division," VLSI Test Symposium, IEEE, pp. 0207, 20th IEEE VLSI Test Symposium, 2002.

	BibTex	x
	@article{ 10.1109/VTS.2002.1011140, author = {Takahiro J. Yamaguchi and Masahiro Ishida and Mani Soma and Louis Malarsie and Hirobumi Musha}, title = {Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2002}, isbn = {0-7695-1570-3}, pages = {0207}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011140}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division SN - 0-7695-1570-3 SP EP A1 - Takahiro J. Yamaguchi, A1 - Masahiro Ishida, A1 - Mani Soma, A1 - Louis Malarsie, A1 - Hirobumi Musha, PY - 2002 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Takahiro J. Yamaguchi, Advantest Laboratories, Ltd.

Masahiro Ishida, Advantest Laboratories, Ltd.

Mani Soma, University of Washington

Louis Malarsie, Agere Systems

Hirobumi Musha, Advantest Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011140

This paper presents a new method fo measuring timing jitter of the bit clock signal in telecommunication devices operating at 10 Gbps. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter. The theory fo this frequency division method is supported by the experimental data from a serializer-deserializer device.

Citation:

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha, "Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division," vts, pp.0207, 20th IEEE VLSI Test Symposium, 2002

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