Test Vector Modification for Power Reduction during Scan Testing

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20th IEEE VLSI Test Symposium

Monterey, California

April 28-May 02

ISBN: 0-7695-1570-3

	ASCII Text	x
	Seiji Kajihara, Koji Ishida, Kohei Miyase, "Test Vector Modification for Power Reduction during Scan Testing," VLSI Test Symposium, IEEE, pp. 0160, 20th IEEE VLSI Test Symposium, 2002.

	BibTex	x
	@article{ 10.1109/VTS.2002.1011128, author = {Seiji Kajihara and Koji Ishida and Kohei Miyase}, title = {Test Vector Modification for Power Reduction during Scan Testing}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2002}, isbn = {0-7695-1570-3}, pages = {0160}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011128}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Test Vector Modification for Power Reduction during Scan Testing SN - 0-7695-1570-3 SP EP A1 - Seiji Kajihara, A1 - Koji Ishida, A1 - Kohei Miyase, PY - 2002 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Seiji Kajihara, Kyushu Institute of Technology

Koji Ishida, Kyushu Institute of Technology

Kohei Miyase, Kyushu Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011128

This paper presents a test vector modification method for reducing power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 an be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 48% of the original test set.

Citation:

Seiji Kajihara, Koji Ishida, Kohei Miyase, "Test Vector Modification for Power Reduction during Scan Testing," vts, pp.0160, 20th IEEE VLSI Test Symposium, 2002

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