loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
20th IEEE VLSI Test Symposium
Testing High-Speed SoCs Using Low-Speed ATEs
Monterey, California
April 28-May 02
ISBN: 0-7695-1570-3
ASCII Text
x 
 
Mehrdad Nourani, James Chin, "Testing High-Speed SoCs Using Low-Speed ATEs," VLSI Test Symposium, IEEE, pp. 0133, 20th IEEE VLSI Test Symposium, 2002.
 
 
BibTex
x
 
@article{ 10.1109/VTS.2002.1011124,
author = {Mehrdad Nourani and James Chin},
title = {Testing High-Speed SoCs Using Low-Speed ATEs},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2002},
isbn = {0-7695-1570-3},
pages = {0133},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011124},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Testing High-Speed SoCs Using Low-Speed ATEs
SN - 0-7695-1570-3
SP
EP
A1 - Mehrdad Nourani,
A1 - James Chin,
PY - 2002
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Mehrdad Nourani, University of Texas at Dallas
James Chin, Texas Instruments,Inc.
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate sending the test patterns and collecting the signatures. An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.
Citation:
Mehrdad Nourani, James Chin, "Testing High-Speed SoCs Using Low-Speed ATEs," vts, pp.0133, 20th IEEE VLSI Test Symposium, 2002
Usage of this product signifies your acceptance of the Terms of Use.