A methodology to characterize thoroughly the defective behavior of CML bipolar gates has been developed. This methodology produced data suitable to guide design for testability in CML circuits. Inductive Fault Analysis (IFA) is first applied to library cell layouts to characterize their sensitivity to realistic defects. The data is then processed by an automatic simulation program that can, according to a list of criteria, classify the defective behavior of all cells. This complete analysis allows a thorough characterization of defective cell behaviors of such a logic family, and helps derive specific testability rules and methods. The proposed methodology is flexible enough to be adapted easily to other logic families.