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19th IEEE VLSI Test Symposium
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals
Marina Del Rey, CA
March 29-April 03
ISBN: 0-7695-1122-8
Takahiro J. Yamaguchi, Advantest Laboratories, Ltd
Masahiro Ishida, Advantest Laboratories, Ltd
Mani Soma, University of Washington
David Halter, Motorola Inc.
Rajesh Raina, Motorola Inc.
Jim Nissen, Motorola Inc.
This paper introduces the extended ΔΦmethod for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relationship between cycle-to-cycle period jitter and timing jitter. To validate the method, experimental data from jitter measurements on a PowerPCTM microprocessor is analyzed in the frequency domain. Comparisons of phase quantization errors are made between the extended ΔΦmethod and the conventional zero-crossing method.
Citation:
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen, "A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals," vts, pp.0102, 19th IEEE VLSI Test Symposium, 2001
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