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19th IEEE VLSI Test Symposium
Multiple Scan Chain Design for Two-Pattern Testing
Marina Del Rey, CA
March 29-April 03
ISBN: 0-7695-1122-8
ASCII Text
x 
 
llia Polian, Bernd Becker, "Multiple Scan Chain Design for Two-Pattern Testing," VLSI Test Symposium, IEEE, pp. 0088, 19th IEEE VLSI Test Symposium, 2001.
 
 
BibTex
x
 
@article{ 10.1109/VTS.2001.923423,
author = {llia Polian and Bernd Becker},
title = {Multiple Scan Chain Design for Two-Pattern Testing},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2001},
isbn = {0-7695-1122-8},
pages = {0088},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923423},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Multiple Scan Chain Design for Two-Pattern Testing
SN - 0-7695-1122-8
SP
EP
A1 - llia Polian,
A1 - Bernd Becker,
PY - 2001
KW - Design for test
KW - Delay testing
KW - Scan chain insertion
KW - Core-based test.
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
llia Polian, Institute of Computer Science
Bernd Becker, Albert-Ludwigs-University
Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.
Index Terms:
Design for test, Delay testing, Scan chain insertion, Core-based test.
Citation:
llia Polian, Bernd Becker, "Multiple Scan Chain Design for Two-Pattern Testing," vts, pp.0088, 19th IEEE VLSI Test Symposium, 2001
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