A flip-flop with a reset line makes it easily controllable and initializable, which can greatly reduce test generation time and test sequence length. A partial reset method combined with observation point insertion is presented for synchronous sequential circuits based on a testability measure with respect to iteratively calculated circuit state information and conflict analyses. Partial reset flip-flop selection according to a circuit-state-information-based measure and conflict analysis can break critical cycles of the circuit, make the circuit easy-to-initialize, and reduce potential conflicts in sequential A TPG. The most important reason why previous partial reset methods cannot completely improve testability is that partial reset flip-flops are not controlled by independent reset signals. Testability can be enhanced greatly when partial reset flip-flops are judiciously controlled by independent reset lines. A new testability structure is proposed to design a partial reset flip-flop, which makes the method economical in area, pin and delay overheads. It is demonstrated that a combination of partial reset and observation point insertion can be an attractive alternative to scan design, which presents at-speed test.