A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency

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	Similar Articles Articles by Muhammad Nummer Articles by Manoj Sachdev

19th IEEE VLSI Test Symposium

Marina Del Rey, CA

March 29-April 03

ISBN: 0-7695-1122-8

	ASCII Text	x
	Muhammad Nummer, Manoj Sachdev, "A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency," VLSI Test Symposium, IEEE, pp. 0068, 19th IEEE VLSI Test Symposium, 2001.

	BibTex	x
	@article{ 10.1109/VTS.2001.923420, author = {Muhammad Nummer and Manoj Sachdev}, title = {A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1122-8}, pages = {0068}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923420}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency SN - 0-7695-1122-8 SP EP A1 - Muhammad Nummer, A1 - Manoj Sachdev, PY - 2001 KW - Delay-fault testing KW - high-performance testing KW - design for delay testability KW - built-in self test KW - controlled-delay flip-flop. VL - 0 JA - VLSI Test Symposium, IEEE ER -

Muhammad Nummer, University of Waterloo

Manoj Sachdev, University of Waterloo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923420

This paper presents a methodology for testing high-performance circuits with a low-speed clock in test mode. Using this technique, the frequency of the 50% duty cycle test mode clock can be reduced with virtually no lower limit. This poses very little requirements on automatic test equipment (ATE) and facilitates the testing process. A CMOS implementation that achieves 50ps accuracy is also presented. This technique targets designs using design for testability (DFT) and/or built-in self test (BIST) techniques.

Index Terms:

Delay-fault testing, high-performance testing, design for delay testability, built-in self test, controlled-delay flip-flop.

Citation:

Muhammad Nummer, Manoj Sachdev, "A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency," vts, pp.0068, 19th IEEE VLSI Test Symposium, 2001

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