We present an efficient space compaction method which propagates all realistic errors that can appear at the outputs of a circuit under test in response to a precomputed test set. Since the proposed method does not rely on structural information of the circuit under test, it can be readily applied to intellectual property (IP) cores. Space compaction of test responses for IP cores provides parallel access to their functional outputs and reduces testing time. A d-bounded-weight error model is combined with a d-response graph model to generate the logic specification for the compactor via graph coloring. Moreover, a carefully-chosen subset of inputs of the circuit under test allows error propagation to be achieved using an arbitrarily small number of compactor outputs. The error-bound variable d parametrizes the space compactor, and the synthesis approach can be used to design several space compactors for the same circuit under test by simply varying d. We illustrate the proposed method by presenting experimental results on compactor synthesis for several large ISCAS benchmark circuits.