loading...
Advanced Search 
18th IEEE VLSI Test Symposium (VTS'00)
Montreal, Canada
April 30-May 04
ISBN: 0-7695-0613-5
Table of Contents
Reviewers (PDF)
pp. xxvii
Plenary Session
Program Introduction
Invited Presentation: Wall Street Perspective on System-on-Chip and Test Technology
Session 1: Microprocessor Test/Validation
Narayanan Krishnamurthy, Motorola ASP Somerset Design Center
Andrew K. Martin, Motorola ASP Somerset Design Center
Magdy S. Abadir, Motorola ASP Somerset Design Center
Jacob A. Abraham, University of Texas at Austin
pp. 9
Wei-Cheng Lai, University of California at Santa Barbara
Angela Krstic, University of California at Santa Barbara
Kwang-Ting (Tim) Cheng, University of California at Santa Barbara
pp. 15
Session 2: Low Power BIST and Scan
D. Gizopoulos, University of Piraeus
N. Kranitis, II&T, NCSR ?Demokritos?
M. Psarakis, II&T, NCSR ?Demokritos?
A Paschalis, University of Athens
Y. Zorian, LogicVision
pp. 23
Fulvio Corno, Politecnico di Torino
Maurizio Rebaudengo, Politecnico di Torino
Matteo Sonza Reorda, Politecnico di Torino
Giovanni Squillero, Politecnico di Torino
Massimo Violante, Politecnico di Torino
pp. 29
Session 3: Technology Trends and Their Impact on Test
Session 4: Scan Related Approaches
Frank P. Higgins, Bell Laboratories, Lucent Technologies
Rajagopalan Srinivasan, Bell Laboratories, Lucent Technologies
pp. 67
Abhijit Jas, University of Texas at Austin
Bahram Pouya, University of Texas at Austin
Nur A. Touba, University of Texas at Austin
pp. 73
Session 5: Defect Driven Techniques
Session 6: System-on-chip Test Techniques
A. Bommireddy, Level One Communications
J. Khare, Level One Communications
S. Shaikh, Level One Communications
S-T. Su, Level One Communications
pp. 121
Session 7: Analog Test Techniques
Sule Ozev, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 149
Session 8: BIST: Arithmetic, Memories and ILAs
SPECIAL SESSION 2: Embedded Tutorial
Session 9: Temperature and Process Drift Issues
Chao-Wen Tseng, Stanford University
Edward J. McCluskey, Stanford University
Xiaoping Shao, Intel Corporation
David M. Wu, Intel Corporation
pp. 183
J. Altet, Polytechnical University of Catalonia (UPC)
A. Rubio, Polytechnical University of Catalonia (UPC)
E. Schaub, Universite Bordeaux 1
S. Dialhaire, Universite Bordeaux 1
W. Claeys, Universite Bordeaux 1
pp. 189
Amy Germida, University of Maryland at Baltimore County
James Plusquellic, University of Maryland at Baltimore County
pp. 195
Session 10: Test Compaction and Design Validation
Session 11: Analog BIST
Jan Arild Tofte, Mentor Graphics Corporation
Chee-Kian Ong, University of California at Santa Barbara
Jiun-Lang Huang, University of California at Santa Barbara
Kwang-Ting (Tim) Cheng, University of California at Santa Barbara
pp. 237
M. Renovell, Universit? de Montpellier II
F. Azaïs, Universit? de Montpellier II
S. Bernard, Universit? de Montpellier II
Y. Bertrand, Universit? de Montpellier II
pp. 247
Session 12: Functional Test and Verification Issues
Li Chen, University of California at San Diego
Sujit Dey, University of California at San Diego
pp. 255
A. Jain, Intel Corp.
V. Boppana, Fujitsu Labs. of America, Inc.
R. Mukherjee, Fujitsu Labs. of America, Inc.
J. Jain, Fujitsu Labs. of America, Inc.
M. ~Fujita, Fujitsu Labs. of America, Inc.
M. Hsiao, Rutgers University
pp. 263
Session 13: Memory Test
Chi-Feng Wu, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Kuo-Liang Cheng, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 291
J. Zhao, Texas A&M University
S. Irrinki, LSI Logic Inc.
M. Puri, LSI Logic Inc.
F. Lombardi, Northeastern University
pp. 297
Session 14: Open Defect Detection, Diagnosis and Analog BIST
Victor H. Champac, National Institute for Astrophysics, Optics and Electronics
Antonio Zenteno, National Institute for Astrophysics, Optics and Electronics
pp. 305
SPECIAL SESSION 3: Open Projector
SPECIAL SESSION 5: Panel
B. Vinnakota, University of Minnesota
Andre Ivanov, University of British Columbia
pp. 329
Session 15: Delay Test, Diagnosis and BIST
Manish Sharma, University of Illinois at Urbana-Champaign
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 333
Session 16: BIST Issues
Laurent Brehelin, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Olivier Gascuel, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Gilles Caraux, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Patrick Girard, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Christian Landrault, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
pp. 359
Ilker Hamzaoglu, University of Illinois at Urbana-Champaign
Janak H. Patel, University of Illinois at Urbana-Champaign
pp. 369
Session 17: STIL Extension, Jitter, and Crosstalk
Takahiro J. Yamaguchi, Advantest Laboratories, Ltd.
Masahiro Ishida, Advantest Laboratories, Ltd.
Mani Soma, University of Washington
Toshifumi Watanabe, Advantest Corporation
Tadahiro Ohmi[4], Tohoku Universityapan
pp. 395
Session 18: High Level ATPG and Test Scheduling
F. Ferrandi, Politecnico di Milano
G. Fornara, Politecnico di Milano
D. Sciuto, Politecnico di Milano
G. Ferrara, Siemens Information and Communication Networks
F. Fummi, Universit? di Verona
pp. 423
Session 19: IDDQ Test
Theo J. Powell, Texas Instruments, Inc.
James Pair, Texas Instruments, Inc.
Melissa St. John, Texas Instruments, Inc.
Doug Counce, Texas Instruments, Inc.
pp. 439
Session 20: On-line Testing and Fault Tolerance
Yiorgos Makris, University of California at San Diego
Ismet Bayraktaroglu, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 459
SPECIAL SESSION 7: Panel
F. Muradali, Agilent Technologies
A. Ivanov, University of British Columbia
pp. 471
SPECIAL SESSION 8: Panel
Usage of this product signifies your acceptance of the Terms of Use.