We propose a novel BIST technique for non-scan sequential circuits that does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence generator capable of reproducing the essential features of a set of precomputed deterministic test sequences. We use for this purpose two new models called Hidden Markov Model with Patterns and Independence Model with Patterns. Compared to existing methods, the proposed technique exhibits very high fault coverage, including performance testing, at the expense of a low silicon area overhead.