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18th IEEE VLSI Test Symposium (VTS'00)
Detection of Inter-Port Faults in Multi-Port Static RAMs
Montreal, Canada
April 30-May 04
ISBN: 0-7695-0613-5
J. Zhao, Texas A&M University
S. Irrinki, LSI Logic Inc.
M. Puri, LSI Logic Inc.
F. Lombardi, Northeastern University
This paper deals with testing of inter-port faults in multi-port Static Random Access Memories (SRAMs). A inter-port fault is caused by a short between word/bit lines of different ports in a multi-port SRAM. By considering different implementations of the SRAM and its layout, an approach, which achieves 100 % coverage of fault detection, is proposed.This two-step approach is based on two novel algorithms, MMCA (Modified March C Algorithm) and WIPD (Write Inter-Port Detection). It is shown that inter-port fault detection is a combinatorial problem; hence, MMCA and WIPD must be executed multiple times depending on the types, number of ports and line arrangement in the layout.
Citation:
J. Zhao, S. Irrinki, M. Puri, F. Lombardi, "Detection of Inter-Port Faults in Multi-Port Static RAMs," vts, pp.297, 18th IEEE VLSI Test Symposium (VTS'00), 2000
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