ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits

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18th IEEE VLSI Test Symposium (VTS'00)

Montreal, Canada

April 30-May 04

ISBN: 0-7695-0613-5

	ASCII Text	x
	Hussain Al-Asaad, John P. Hayes, "ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits," VLSI Test Symposium, IEEE, pp. 221, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843849, author = {Hussain Al-Asaad and John P. Hayes}, title = {ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {221}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843849}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits SN - 1093-0167 SP EP A1 - Hussain Al-Asaad, A1 - John P. Hayes, PY - 2000 KW - Design validation KW - error modeling KW - error and fault simulation KW - critical path tracing VL - 0 JA - VLSI Test Symposium, IEEE ER -

Hussain Al-Asaad, University of California at Davis

John P. Hayes, University of Michigan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843849

ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of simulation algorithms based on parallel-pattern evaluation, multiple error activation, single fault propagation, and critical path tracing. Several experiments are discussed to demonstrate the power of ESIM.

Index Terms:

Design validation, error modeling, error and fault simulation, critical path tracing

Citation:

Hussain Al-Asaad, John P. Hayes, "ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits," vts, pp.221, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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