Space compaction of test responses provides parallel access to functional outputs and reduces delays on functional paths between cores. We present a new space compaction approach for IP cores that only uses information about the fault-free responses for a precomputed test set T. It does not make any assumption about an underlying fault model, and it does not make use of any structural information about the core.Advantages of this approach include zero aliasing for all errors and optimum (provably maximum) compaction ratio. The compactor design is based on the use of orthogonal transmission functions, which allow all errors produced by T to be propagated through the space compactor. We illustrate the proposed method by presenting case studies on compactor synthesis for several ISCAS benchmark circuits.