SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration

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18th IEEE VLSI Test Symposium (VTS'00)

Montreal, Canada

April 30-May 04

ISBN: 0-7695-0613-5

	ASCII Text	x
	Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy, "SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration," VLSI Test Symposium, IEEE, pp. 205, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843847, author = {Xijiang Lin and Wu-Tung Cheng and Irith Pomeranz and Sudhakar M. Reddy}, title = {SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {205}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843847}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration SN - 1093-0167 SP EP A1 - Xijiang Lin, A1 - Wu-Tung Cheng, A1 - Irith Pomeranz, A1 - Sudhakar M. Reddy, PY - 2000 KW - Synchronous Sequential Circuits; Static Test Compaction; Test Segment; Parallel Pattern Simulator; Vector Restoration; Single Fault Restoration; Test Length; Fault Coverage VL - 0 JA - VLSI Test Symposium, IEEE ER -

Xijiang Lin, Mentor Graphics Corporation

Wu-Tung Cheng, Mentor Graphics Corporation

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843847

We propose a new approach for implementing static compaction procedures for synchronous sequential circuits. The procedures we consider belong to the class of procedures that generate the compacted test sequence through restoration of segments (or subsequences) of a given test sequence T. Under the proposed approach, each restored segment detects a single target fault chosen from the faults detected by T at one time unit. A novel parallel pattern simulator is developed for this purpose. Experimental results for benchmark circuits are included.

Index Terms:

Synchronous Sequential Circuits; Static Test Compaction; Test Segment; Parallel Pattern Simulator; Vector Restoration; Single Fault Restoration; Test Length; Fault Coverage

Citation:

Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy, "SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration," vts, pp.205, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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