loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
18th IEEE VLSI Test Symposium (VTS'00)
Cold Delay Defect Screening
Montreal, Canada
April 30-May 04
ISBN: 0-7695-0613-5
Chao-Wen Tseng, Stanford University
Edward J. McCluskey, Stanford University
Xiaoping Shao, Intel Corporation
David M. Wu, Intel Corporation
Delay defects can escape detection during the normal production test flow; particularly if they do not affect any of the long paths included in the test flow. Some delay defects can have their delay increased, making them easier to detect, by carrying out the test with a very low supply voltage (VLV testing). However, VLV testing is not effective for delay defects caused by high resistance interconnects. This paper presents a screening technique for such defects. This technique, cold testing, relies on carrying out the test at low temperature. One particular type of defect, silicide open, is analyzed and experimental data is presented to demonstrate the effectiveness of cold testing.
Index Terms:
Delay Testing, Reliability, Manufacturing quality
Citation:
Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu, "Cold Delay Defect Screening," vts, pp.183, 18th IEEE VLSI Test Symposium (VTS'00), 2000
Usage of this product signifies your acceptance of the Terms of Use.