This paper describes the test challenges faced and testability features implemented on Level One's networking System on Chip (SoC), IXE2000. The IXE2000 SoC is a 20+ million transistor Layer 2/3/4 Switch with 24 IO/IOOMbps and 2 IOOOMbps Ethernet ports, and a predominantly IP-based design. The chip had constraints in terms of both design time and total system costs, which added an extra burden on test. The paper discusses how these constraints led to the current testability solutions and debugs features on the chip.