Boundary-Scan (B-S) strategies require successful coordination of B-S activities for the devices integrated on boards and systems. The original Boundary-Scan Master (BSM) chip was developed to achieve this coordination. We have recently designed the next generation version, named BSM2 that provides a more flexible architecture and a more complete set of features as compared to the original BSM. In this paper, we describe the architectural features of BSM2 device highlighting various scan modes, automatic scan sequencing and gated clock support. We also describe the verification and testing strategies for the design including the backward compatibility with the original BSM features. DFT structures are added to the device to achieve both high fault coverage and self-test capability, as this device forms the test conduit for board and system-level testing. Finally, we briefly discuss the device support for addressable scan port (ASP) protocol and its usage in DSP applications.