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18th IEEE VLSI Test Symposium (VTS'00)
Static Compaction Techniques to Control Scan Vector Power Dissipation
Montreal, Canada
April 30-May 04
ISBN: 0-7695-0613-5
Ranganathan Sankaralingam, University of Texas at Austin
Rama Rao Oruganti, University of Texas at Austin
Nur A. Touba, University of Texas at Austin
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause problems both with heat dissipation and with current spikes. Compacting scan vectors greatly increases the power dissipation for the vectors (generally the power becomes several times greater). The compacted scan vectors often can exceed the power constraints and hence cannot be used.It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced. A static compaction procedure is presented that can be used to find a minimal set of scan vectors that satisfies constraints on both average power and peak power. The proposed approach is simple yet effective and can be easily implemented in the conventional test vector generation flow used in industry today.
Index Terms:
Embedded Cores, Scan Chains, Design-for-Testability, Low Power, Static Compaction, Test Vector Compaction, Built-In Self-Test, Integrated Circuits, Digital Testing, Heat Minimization, Peak power, switching activity
Citation:
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," vts, pp.35, 18th IEEE VLSI Test Symposium (VTS'00), 2000
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