In the last decade, researchers devoted many efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application circuits are subject to an activity level higher than the normal one: the extra power consumption due to test application may thus raise severe hazards to the circuit reliability. Moreover, it can dramatically shorten battery life when periodic testing of battery-powered systems is considered.In this paper, we propose an algorithm to design a Test Pattern Generator based on Cellular Automata for testing combinational circuits that effectively reduces power consumption while attaining high Fault Coverage. Experimental results show that our approach reduces the power consumed during test by 34% on the average, without affecting Fault Coverage, Test Length and area overhead.