This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions. This is because no instruction sequence can produce a test sequence, which can sensitize the path and capture the fault effect into the destination out put/flip-flop at-speed. These paths are called functionally untestable paths.We discuss the impact of delay defects on the functionally untestable paths on the overall circuit performance and illustrate that they do not need to be tested if the delay defect does not cause the path delay to exceed twice the clock period. Under the assumption that delay defects causing the path delay to exceed twice the clock period will be detected by tests for transition faults, the identified functionally untestable paths do not need to be targeted for path delay testing.We describe a method to identify functionally untestable paths. The main components of our method are: (1) using the microprocessor's RTL description, we extract the spatial and temporal correlations among registers and flip-flops in the microprocessor and (2) we use the extracted constraints to identify functionally untestable paths. Identification of such paths helps determine the achievable path delay fault coverage and reduce the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable and thus need not be tested.