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1999 17TH IEEE VLSI Test Symposium
San Diego, California
April 26-April 30
ISBN: 0-7695-0146-X
Table of Contents
Keynote Address
Invited Presentation
Session 1: Testing High-Speed and Dynamic Circuits: Moderators: B. Courtois, TIMA
Session 2: Core Testing: Moderators: R. Garcia, Schlumberger
Session 3: Diagnosis: Moderators: R. Galivanche, Intel
Andreas Veneris, University of Illinois at Urbana
Ibrahim N. Hajj, University of Illinois at Urbana
Srikanth Venkataraman, Intel Corporation
W. Kent Fuchs, Purdue University
pp. 58
Session 4: Techniques for the Very-Deep Submicron: Moderators: L. Bouzaida, ST Microelectronics
Yi-Shing Chang, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A. Breuer, University of Southern California
pp. 95
Session 5: Advanced Scan Path Techniques: Moderators: K. Ruparel, Cisco
Abhijit Jas, University of Texas at Austin
Jayabrata Ghosh-Dastidar, University of Texas at Austin
Nur A. Touba, University of Texas at Austin
pp. 114
Session 6: IDDQ Testing: Moderators: C. Hawkins, University of New Mexico
Session 7: Delay Fault Testing: Moderators: J. Aylor, University of Virginia
Session 8: Validation, Verification, and Diagnosis: Moderators: D. Pradhan, Texas A&M University
Jian Shen, The University of Texas at Austin
Jacob A. Abraham, The University of Texas at Austin
pp. 189
Session 9: Mixed Signal Testing: Moderators: G. Roberts, McGill University
Jiun-Lang Huang, University of California at Santa Barbara
Chen-Yang Pan, University of California at Santa Barbara
Kwang-Ting Cheng, University of California at Santa Barbara
pp. 220
Session 10: BIST: Moderators: S. Wu, Lucent Bell Labs
Janusz Rajski, Mentor Graphics Corporation
Grzegorz Mrugalski, Poznan University of Technology
Jerzy Tyszer, Poznan University of Technology
pp. 236
Session 11: ATPG Related Approaches: Moderators: J. Sprock, Synopsys
Session 12: Testing MEMS, MCM and Analog Circuits: Moderators: D. Keezer, Georgia Tech
Zao Yang, Silicon Graphics Inc.
K.-T. Cheng, University of California at Santa Barbara
K.L. Tai, Bell Laboratories
pp. 290
Session 13: Mixed Signal BIST: Moderators: B. Kaminska, Opmaxx
Sassan Tabatabaei, University of British Columbia
André Ivanov, University of British Columbia
pp. 311
Jinyan Zhang, University of Washington
Sam Huynh, University of Washington
Mani Soma, University of Washington
pp. 319
Session 14: High-Level Test Techniques: Moderators: K. Kinoshita, Osaka University
Session 15: Concurrent Checking: Moderators: J. Huertas, Centro Nacional de Microelec
Session 16: Memory Test: Moderators: C.-W. Wu, Tsing Hua University
Session 17: BIST Related Approaches: Moderators: R. David, Lab d'Automatique de Grenoble
Carter Hamilton, University of Kentucky
Gretchen Gibson, University of Kentucky
Sajitha Wijesuriya, University of Kentucky
Charles Stroud, University of Kentucky
pp. 413
Session 18: Defect Oriented Test: Moderators: Y. Malaiya, Colorado State University
E. Isern, Universit?t Illes Balears
M. Roca, Universit?t Illes Balears
J. Segura, Universit?t Illes Balears
pp. 420
Ankur Jain, Rutgers University
Michael S. Hsiao, Rutgers University
Vamsi Boppana, Fujitsu Labs of America, Inc.
M. Fujita, Fujitsu Labs of America, Inc.
pp. 426
Session 19: On-Line Testing and Fault Tolerance: Moderators: M. Bayoumi, University of Southwestern Louisiana
Ismet Bayraktaroglu, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 446
Session 20: DFT and Boundary Scan: Moderators: S. Mourad, Santa Clara University
Jingjing Xu, University of California at Santa Cruz
Rahul Kundu, University of California at Santa Cruz
F. Joel Ferguson, University of California at Santa Cruz
pp. 460
Special Session 2: IEEE P1500: SOC Test Standardization: Moderator: K. Wagner, Stream Machine
P1500-CTL: Towards a Standard Core Test Language
Embedded Presentation: At-Speed Logic Built-In Self-Test: Moderator: J. Rajski, J. Tyszer
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