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1999 17TH IEEE VLSI Test Symposium
A Systematic DFT Procedure for Library Cells
San Diego, California
April 26-April 30
ISBN: 0-7695-0146-X
ASCII Text
x 
 
Jingjing Xu, Rahul Kundu, F. Joel Ferguson, "A Systematic DFT Procedure for Library Cells," VLSI Test Symposium, IEEE, pp. 460, 1999 17TH IEEE VLSI Test Symposium, 1999.
 
 
BibTex
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@article{ 10.1109/VTEST.1999.766704,
author = {Jingjing Xu and Rahul Kundu and F. Joel Ferguson},
title = {A Systematic DFT Procedure for Library Cells},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1999},
issn = {1093-0167},
pages = {460},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766704},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - A Systematic DFT Procedure for Library Cells
SN - 1093-0167
SP
EP
A1 - Jingjing Xu,
A1 - Rahul Kundu,
A1 - F. Joel Ferguson,
PY - 1999
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Jingjing Xu, University of California at Santa Cruz
Rahul Kundu, University of California at Santa Cruz
F. Joel Ferguson, University of California at Santa Cruz
We present an automated procedure for improving the testability of a product by improving the testability of cells in the cell library. This method was applied to a scan flip-flop from Cyrix's standard cell library. Based on this analysis, some design and layout changes were suggested, which brought down the probability of difficult-to-detect faults by 70%, without compromising the performance or increasing the area of the circuit.
Citation:
Jingjing Xu, Rahul Kundu, F. Joel Ferguson, "A Systematic DFT Procedure for Library Cells," vts, pp.460, 1999 17TH IEEE VLSI Test Symposium, 1999
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