loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
1999 17TH IEEE VLSI Test Symposium
Defect-Oriented Test Scheduling
San Diego, California
April 26-April 30
ISBN: 0-7695-0146-X
Wanli Jiang, University of Minnesota
Bapiraju Vinnakota, University of Minnesota
Test time can be reduced by ordering tests so as to fail defective units early in the test process. An ordering algorithm requires information on the ability of tests to detect defective units. We obtain it by applying all possible tests to a small subset of manufactured units and assuming the information obtained from this sub-set is representative. We develop a simple polynomial-time heuristic which uses the information from the sample set to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. Optimal test ordering algorithms require execution time which is exponential in the number of tests applied. In our experiments, the heuristic results in a significant reduction in test time for manufactured digital and analog ICs.
Citation:
Wanli Jiang, Bapiraju Vinnakota, "Defect-Oriented Test Scheduling," vts, pp.433, 1999 17TH IEEE VLSI Test Symposium, 1999
Usage of this product signifies your acceptance of the Terms of Use.